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1735 n. first st. #308, san jose, ca 95112, tel (408)451-1400, fax (408)451-1404 1 system controller for i960jx processors gt- 32090 preliminary, rev. 2.0 march 1996 galileo technology, inc. ? integrated system controller for embedded applica- tions ? supports the i960jx family of cpus ? 16-33mhz bus frequency ? flexible dram controller - page mode and edo drams - 128mbyte address space - 256k-4m device depth - 1-4 banks supported directly - up to 8 banks supported indirectly - 32-bit data width - non-interleaved - different size for each bank - zero wait state to first data at 16 and 20mhz - one wait state to first data and no wait state to burst data at 25mhz - two wait states to first data and no wait state to burst data at 33mhz ? flexible ad bus device controller - 128mbyte address space - 4 chip selects - per bank programmable timing - supports several types of standard memories (rom / flash / sram) and i/o controllers - external wait support - 8-, 16-, and 32-bit device (and boot) support ? high performance dma - three independent channels - chaining via linked lists of records - transfers through a 16-byte internal fifo or fly-by - moves data between sio, memory, and devices - packing and unpacking of 8-bit and 16-bit data to/ from the sio bus into 32-bit data on the cpu bus - packing and unpacking from/to the sio bus con- current with ad bus activity - fixed and round robin programmable priorities ? simple i/o bus (sio bus) - simple read/write bus for glueless interface to low cost peripherals - 8/16-bit wide bus - four chip selects - programmable timing - external wait support ? pcmcia - supports two pcmcia devices directly ?jtag ?5v ? 160 pqfp features note: always contact galileo technology for possible updates before starting a design. i960jx dram GT-32090 scsi network sio bus ad bus address & 373 32 16 flash uart external agent adbusreq adbusgnt control control pcmcia card control address data
GT-32090 system controller for i960jx processors 2 galileo technology, inc. overview the GT-32090 is a low cost, highly integrated single-chip system controller for the i960jx family. it provides high system performance, while reducing cost, complexity, device count, and board space. the GT-32090 controls two separate and independent buses, the cpus 16 to 33mhz 32-bit wide address/data bus, and a 16-bit i/o bus. the two buses can work concurrently at different fre- quencies. the dram controller supports up to 128mbytes of stan- dard or edo dram. it supports up to four 32-bit wide banks directly, or up to eight banks indirectly, with zero wait states to first data or burst data at 16 and 20mhz. at 25 and 33mhz, there is one wait state and two wait states respectively, to first data, and at both frequencies there are no wait states to burst data. various refresh and addressing modes are supported. the device controller supports up to 4 devices directly, and includes various programmable timing and wait state mechanisms that can be setup individually for each device. typical devices supported include dram, rom, flash, and sram, as well as high-performance master peripherals. the powerful three-channel dma controller has data alignment capabilities and sophisticated chaining support via link lists. the dma can move data between devices on the cpu bus, or between devices on the cpu bus and devices on the i/o bus. dma transfers can go through an on-board 16-byte fifo, or directly if in fly-by mode. packing and unpacking of 8-bit and 16-bit data from/to the i/o bus occurs concurrently with activity on the cpu bus, increasing overall system bandwidth. the i/o bus is a simple 16-bit read/write bus that inter- faces to a large variety of low cost support components like uarts, scsi controllers, ethernet controllers, and other devices. the i/o bus supports 8- or 16-bit peripher- als, as well as slave dma and pcmcia devices. three 4- byte fifos provide efficient support for the gathering of 8-bit or 16-bit data to/from different peripherals, in the endianess chosen by the designer. the GT-32090 includes a direct interface to two 8-bit or 16-bit pcmcia slots. reference design galileo makes available the galileo-5 evaluation and development system, an isa card which greatly facili- tates the development of embedded control systems based on the i960ja/jd/jf intel processors. the centerpiece of the system is the GT-32090 system controller, which integrates most of the core logic neces- sary in embedded applications. the galileo-5 board serves two main objectives: a) it allows customers to easily evaluate the performance of a GT-32090 based system, using their own software, as opposed to generic benchmarks. b) it greatly facilitates and expedites the development of the final product, since hardware designers can use its design as a reference and software designers can use it to start porting software ahead of their own hardware platform. the shipping configuration of the galileo-5 includes a 33mhz i960ja cpu, 4mbytes of dram, sockets for 2mbytes of flash, a 512kbyte eprom, a duart, intel mon960 software, and 2 pcmcia sockets. jumpers allow customers to evaluate a large variety of system configurations, and expansion connectors allow cus- tomer-designed options to be easily interfaced to. the galileo-5 can either be used in stand-alone fashion, or it can be plugged directly into an isa slot of standard personal computers. cpu interface 16 byte fifo ad bus device controller dram controller 16-bit i/o bus 4-byte gathering fifo i/o arbiter dma arbiter jtag 4-byte gathering fifo 4-byte gathering fifo 16-bit bypass path byte alignment sio device control pcmcia control linked list control dma channel 2 dma channel 1 dma channel 3
GT-32090 system controller for i960jx processors 3 galileo technology, inc. 1 pin information 1.1 logic symbol rst* p/sdata[15:0] sbe[1:0]* devcs[2:0]* dwr* dadr[10:0] 11 ras[3:0]* 4 4 3 GT-32090 cas[3:0]* ready* misc. pcmcia 16 2 dmareq[2:0] p/saddr[1:0] holda hold rdyrcv* ad[31:0] be[3:0]* cpu ads* w/r* ale 4 32 dram device dmaack[2:0]* bufoe* 3 3 scs[3:0]* 4 swr* srd* swait* iowra* iorda* waita* wrena* oea* cardena[2:1]* 2 cardenb[2:1]* 2 jtdi 4 wren[3:0]* le* lrdoe* adbusreq adbusgnt dma sio bootcs* iowrb* iordb* waitb* wrenb* oeb* card a pcmcia card b 3 dmaint[2:0]* clock jtag jtclk jtms jtrst* jtdo 2 scan test* hizall* lwroe*
GT-32090 system controller for i960jx processors 4 galileo technology, inc. 1.2 pin assignment table pin name type description cpu interface ad[31:0] i/o address/data bus: multiplexed address and data bus for commu- nication between the processor, devices, dram, any external agent, and the GT-32090. ale i/o address latch enable: a strobe for latching the address into the GT-32090 and into external latches for devices, pcmcia cards, and sio bus peripherals. it is an input during a cpu or external agent access, and an output during a dma access. ads* i/o address strobe : indicates a valid address and the start of a new bus access. it is an input during a cpu or external agent access, and an output during a dma access. be[3:0]* i/o byte enable: selects which of the four bytes on the ad bus partici- pate in the current bus access. it is an input during a cpu or exter- nal agent access, and an output during a dma access. hold o hold : a request from the GT-32090 to acquire the ad bus. holda i hold acknowledge: an indication by the cpu that it has relin- quished the ad bus to the GT-32090. rdyrcv* o ready/recover : indicates when the data on the ad bus can be sampled or removed. during a device turn-off time, it indicates to the cpu not to drive the address on the ad bus. w/r* i/o write/read: specifies if the access is a write or a read access. it is an input during a cpu or external agent access, and an output dur- ing a dma access. used also to control the direction of the bi-direc- tional transceiver for the devices on the ad bus. dram dadr[10:0] o dram address/device burst address : eleven multiplexed address bits to the dram. dadr[1:0] provides the word burst address (same meaning as the cpus a3, a2 pins) for all 32-bit accesses, be they to dram or to devices. ras[3:0]* o row address select : supports four banks of dram. cas[3:0]* o column address select: supports byte writes to dram. dwr* o dram write: signals a write access to the dram. le* o latch enable: when active, latches the dram data into external latches. lrdoe* o latch read output enable: when active, outputs the data from the drams external latches onto the ad bus. lwroe* o latch write output enable: when active, outputs the data from the drams external latches onto the drams data pins. ad bus devices wren[3:0]* o write enable: byte write enable to devices on the ad bus. devcs[2:0]* o device chip select : programmable chip select signals to devices on the ad bus. bootcs* o boot chip select : programmable chip select signal to the boot device on the ad bus.
GT-32090 system controller for i960jx processors 5 galileo technology, inc. ready* i ready : when not active, it extends the access to a device on the ad bus by adding wait cycles. bufoe* o buffer output enable: this signal has similar functionality to the den* signal of the i960jx, but is active during accesses to devices only. it is active during the data phase of accesses to devices on the ad bus. it is used with the w/r* to control external data transceiv- ers. pcmcia & sio shared signals p/saddr[1:0] o pcmcia/sio address : byte and half-word addresses for pcmcia and sio accesses. p/sdata[15:0] i/o data bus: shared data bus for sio and pcmcia devices. sio interface sbe[1:0]* o sio byte enable: selects which of the two bytes on the sio bus participates in the current data transfer. scs[3:0]* o sio chip select: chip select for devices on the sio bus. srd* o sio read: active during a read from a device on the sio bus. swr* o sio write: active during a write to a device on the sio bus. swait* i sio wait: extends bus cycle, used to generate wait states by sio devices. pcmcia card a cardena[2:1]* o card enable a: cardena[1] enables the even address bytes, and cardena[2] enables the odd address bytes. oea* o output enable a: controls the output of data from card. waita* i wait a: extends bus cycle, used to generate wait states by the card. wrena* o write enable a: indicates write accesses by the GT-32090 to the card. iorda* o i/o read a: activated to read data from the cards i/o space. iowra* o i/o write a : activated to write data to the cards i/o space. pcmcia card b cardenb[2:1]* o card enable b: cardenb[1] enables the even address bytes, and cardenb[2] enables the odd address bytes. oeb* o output enable b: controls the output of data from card. waitb* i wait b: extends bus cycle, used to generate wait states by the card. wrenb* o write enable b: indicates write accesses by the GT-32090 to the card. iordb* o i/o read b: activated to read data from the cards i/o space. iowrb* o i/o write b : activated to write data to the cards i/o space. dma adbusreq i bus request: signals a request from the external agent to the gt- 32090 for acquisition of the ad bus. pin name type description
GT-32090 system controller for i960jx processors 6 galileo technology, inc. adbusgnt o bus grant: signals that the GT-32090 grants mastership on the ad bus to the external agent. dmareq[2:0] i dma request: a request for a dma operation directed at the inter- nal arbiter. when rst* is asserted these bits are sampled into the device address space register bits [6:4]. dmaack[2:0]* i/o dma acknowledgement: outputs - the internal arbiter grants a dma operation to a request- ing device. inputs - when rst* is asserted, these bits are sampled into the internal space decode & control register bits [5:3]. these pins are inputs when rst* is active, until 2 clocks after rst* is deasserted. they are outputs at all other times. dmaint[2:0]* o interrupt: each interrupt corresponds to one of the dma channels. miscellaneous rst* i reset: resets all internal logic and state machines to a known state. clock i clock: the input clock to the GT-32090. jtag jtdi i test data input pin: jtags serial input jtms i test mode select: used to issue serial instructions to the tap con- trollers state machine. jtclk i test clock: jtags input clock jtrst* i test reset: active low asynchronous reset for the tap controller jtdo o test data output: jtags serial output scan te s t * i te st: when active, indicates that the GT-32090 is in scan mode. 0 - scan mode 1 - normal operation hizall* i tri-state: when active, the GT-32090 drives all outputs and i/o pins to high impedance. 0 - tri-state 1 - normal operation pin name type description
GT-32090 system controller for i960jx processors 7 galileo technology, inc. 2 functional description 2.1 cpu interface the GT-32090 has a glueless interface to the intel i960jx family of processors with bus frequencies between 16mhz and 33mhz. external agents can take control of the ad bus and access all of the GT-32090 resources. the GT-32090 handles the priorities between the internal dma resources, the cpu and the external agent. it will request the ad bus from the cpu and relin- quish the bus to the external agent. for systems that need extension of the capabilities offered by the gt- 32090, up to four GT-32090 devices can support one cpu. for example, with four GT-32090s, the system can have up to 512mbytes of dram and 12 dma channels. 2.2 address space decode the GT-32090 decodes the address space in two stages. in the first stage, the decoding is done to eight groups that include the following: four spaces of 32 mbytes for the ad bus devices, 128 mbytes for the dram, 128 mbytes for the simple i/o bus (sio bus), 256 mbytes for the pcmcia, and 64 mbytes for the internal address space. the decoding in the first stage is done by compar- ing the high order address bits with the address space registers values. this way, four groups of devices are provided in order to enable mappings of 8-, 16- and 32- bit devices in the same system, using different pmcons (pmcons are the i960jxs physical memory configura- tion registers - see i960jx users manual). in the second stage, there is additional decoding to the specific device bank, dram bank, internal register, sio bank, or pcm- cia bank. the sub-decoding for the dram and the ad bus device banks is programmable while the sub-decod- ing for the internal registers, the pcmcia cards, and the sio devices, is fixed. each dram bank can have a programmable address space of 1mbyte to 16mbytes that can be located any- where in the dram address space. the address space size programmability enables a contiguous address space when accessing the different dram banks even when the banks have different sizes. the decoding is done by comparing address bits 25:20 to be between two values (high and low) in the dram bank registers. each ad bus device bank can have a programmable address space of 2mbytes to 32mbytes. similar to the dram banks, it enables a contiguous address space for different ad device bank sizes. the decoding is done by comparing address bits 24:21 to be between two values (high and low) in the ad device bank registers. the pcmcia is allocated a 256mbyte block that has a fixed sub-decoding to four 64mbyte spaces. the first 128mbytes are allocated to card a and the second 128mbytes to card b. each 128mbytes are divided so that the first 64mbytes are for memory space and the second 64mbytes are for i/o address space. the sio space is sub-decoded to four fixed 16 mbyte spaces for the sio chip selects, or eight 16mbyte spaces with external sub-decoding to create a 128mbyte space. the internal address space is sub-decoded for the con- trol and status registers that reside on the GT-32090. the GT-32090 will not respond to addresses that are not allocated to it, since that address space might be used for other devices. 2.3 dram controller the dram controller supports 4 banks of page mode or edo drams. dram types supported are those with 0.5k, 1k, and 2k refresh, as well as asymmetric ras/ cas addressing. the depth of the dram devices can vary for each bank separately from 256k to 4m, and the width of all banks is 32-bits. with these options, each dram bank size can vary from 1mbyte to 16mbytes. the dram timing is optimized for the different frequen- cies and device types supported. there is optional sup- port for an external bi-directional latch on the drams data bus for improved dram performance. at 33mhz, a cpu read access from an edo dram will have the pattern xxdddd, which means 2 wait-states to first data and zero wait-state for each additional word. at 33mhz, with standard drams, the pattern will be xxdxdxdxdx, meaning 2 wait-states to the first data and 1 wait-state for each additional word. at 25mhz, standard dram with latch or edo dram will have a performance of xdddd (one wait-state to first data). at 25mhz, stan- dard dram without latches will be xxdxdxdxdx (2 wait- states to first data, 1 wait-state to burst data. at 20mhz and 16mhz using standard dram with latches or edo dram, the pattern will be dddd, zero wait-states to the first data and zero wait-states for each additional word. at 20mhz and 16mhz, dram performance is xxdxdxdxdx. dma burst accesses can be one per clock, using the same parameters as for the cpu access. refresh can be programmed to different periods by a 16- bit refresh counter. staggered and non-staggered refresh modes are supported. in staggered mode, the four banks of dram will be refreshed with one cycle delay between each bank, while in non-staggered mode all four banks will be refreshed together.
GT-32090 system controller for i960jx processors 8 galileo technology, inc. for systems that require more than 64mbytes of dram, it is possible to add 4 more dram banks with a simple external multiplexer, to get to a total of 128mbytes of dram with 8 ras control signals, using address[26] to multiplex between two banks. for instance, the demulti- plexing can be implemented with a quality semiconduc- tor qs3257. 2.4 ad bus device controller the GT-32090 supports directly four devices on the ad bus, one boot device and three general purpose devices such as flash, sram, rom, fifo, or any other read/ write peripheral device. external logic can sub-decode the four chip selects to any number, using the address for the sub-decoding. the device controller has several con- trol signals to enable read and write accesses (including chip selects, reads, writes, and buffer control). each chip select has a programmable address space of 2mbytes to 32mbytes to enable contiguous address space between the different banks. byte writes are enabled through four write enable signals. the write signals can be shaped by specifying in the device bank parameters registers the following: the number of cycles from the assertion of devcs* to the first assertion of write (cstowr); the num- ber of cycles the write pulse is active (wractive); and the number of cycles the write signal is non-active between consecutive writes(wrhigh). the timing parameters of the write signals determine the length of active devcs* and dmaack* (when allocated to an ad bus device). in read cycles, the following parameters are programma- ble: the number of cycles from the assertion of chip select to the rising edge of the clock that samples the first data (delaytofirst), the number of cycles from when data is sampled to the next time data is sampled (delay- tonext); and the number of cycles between the deasser- tion of devcs* to a new ad bus cycle (turnoff). each device can be configured as 8-, 16- or 32-bits wide, by programming the appropriate i960jxs pmcon regis- ter to the desired bus width, and mapping the appropriate device n address space decode register into this address space. each pmcon configures the bus width of a memory region with a specific addr[31:29] while the device n address space decode register maps device #n into a region with a specific addr[31:25]. the device controller supports read or write bursts of up to four data elements. the burst address is supported by a 2-bit wide address bus that is multiplexed with the two least significant bits of the dram address (dadr[1:0]) when the device is 32-bits wide. for an 8-bit device the burst address is the cpus be[1:0]*, and for a 16-bit device the burst address is the cpus {a2, be[1]*}. for an 8-bit device the write signal is wren[0]*, and for a 16- bit device the write signals are wren[3]* (write high byte) and wren[0]* (write low byte). the ready* pin enables an extension of a device cycle beyond the values that are programmed in the device bank parameters register. all the control signals will con- tinue to be in their state when the ready* signal is sam- pled inactive, and until it becomes active. the internal state machine counters will continue to count to the pro- grammed values, even when ready* is high. the con- trol signals will change only when the ready* is low and the counters are at terminal count. after insertion of wait states and re-assertion of ready*, there are two clock cycles to data transfer. the use of the ready* signal is individually optional for each bank through a programma- ble bit in the device bank parameters registers. in systems where the devices on the ad bus represent a large load, or where there are devices with long turn-off times, the GT-32090 supports an optional bi-directional transceiver (245 type) to isolate the device bus from the cpus ad bus. the bufoe* signal controls the bi-direc- tional transceivers oe* and the w/r* signal controls its direction. 2.5 dma the dma controller can move data between devices on the ad bus, or between devices on the ad bus and devices on the sio bus. there are two dma subsystems on the GT-32090, one handles the dma activity on the sio bus, and the other handles the activity on the ad bus. each dma subsystem has its own data storage resources and arbiters. the two dma subsystems can work simultaneously or independently, except for the time that they transfer data between the sio bus and the ad bus. both subsystems can have at one time three dma channels active. each of the three channels can be allo- cated to service the sio bus or the ad bus. dma accesses can be initiated by an external request by asserting one of the three dmareq pins (demand mode), or by setting an internal bit in a register (block mode). access can be non-aligned both at the source and at the destination, and up to 64kbytes of data can be transferred in each transaction. the ad bus dma can transfer data in two ways: through an internal 16-byte fifo, or directly between the dram and an ad bus device (fly-by). in the internal mode, data is transferred from the source device/dram into the internal fifo, and from the internal fifo to the destina- tion device/dram. in fly-by mode, the access is to
GT-32090 system controller for i960jx processors 9 galileo technology, inc. dram with assertion of devcs*, dmaack*, and wren*, if necessary. the wren* signals are not toggled. the length of each dma access can be limited to 1, 2, or 4 32-bit words. for a 32-bit device, the write signals are wren[3:0]*. for a 16-bit device, the write signals are wren[3]* for write high byte, and wren[0]* for write low byte. for an 8-bit device, the write signal is wren[0]*. the sio bus dma can transfer data between an 8- or 16- bit wide device on the sio bus, and a 32-bit wide device/ dram on the ad bus. in read accesses (from an sio device to an ad bus device), the sio dma uses one of three internal packing registers (one for each channel), that pack 8- or 16-bit data into 32-bit words. in write accesses (from an ad bus device to an sio device), the sio dma uses one of three internal unpacking registers (one for each channel), that unpack 32-bit words into 8- or 16-bit data. the sio channel can be programmed as read (source) or write (destination) depending on bit 5 of the channel mode register. during an sio dma, data is transferred in two stages that involve one of the sio local packing and unpacking registers, and the fifo in the ad dma unit. during an sio dma read access, the sio device will arbitrate for the sio bus in the local sio arbiter, and will move data into its channel packing register. when the register is full, or when the dma counter reaches terminal count, the packing register will arbitrate in the ad dma arbiter for the ad dma fifo, and will transfer the data to it. when the data is in the fifo, the fifo will request the ad bus and will transfer data to the ad bus device. during an sio dma write access, the ad dma will move data from the ad bus to its internal fifo. from the fifo, it will move the data into the sio unpacking register, and then the sio dma will unpack and transfer the data to the requesting sio device. the sio packing/unpacking register can be flushed by writing to the channel flush/reset register (see section 3.11). the sio channel can be programmed to two possibilities of arbitration: 1) access arbitration: arbitration between sio chan- nels is done in every sio dma access (byte or 16-bit word). 2) word arbitration: arbitration between sio channels is done only when the dma finishes packing/unpacking its register (four byte transfers or two 16-bit word trans- fers). the dma controller supports chained and non-chained modes of operation. in the non-chained mode, the cpu programs the dma channel for each dma transaction. in chained mode, the dma controller programs itself for the next dma operation by fetching the information from a linked list of records in memory. the dma controller can be programmed to assert an interrupt in chained mode, at the end of every dma trans- action or when the next pointer register is null and byte count reaches terminal count. in non-chained mode, the dma will assert an interrupt every time the byte count reaches terminal count. there are two separate arbiters for dma accesses. one arbiter prioritizes accesses between devices on the sio bus for data transfers between sio devices and their packing/unpacking registers. the second arbiter priori- tizes accesses between devices on the ad bus and sio devices. the two arbiters have programmable priorities and are identical in their functionality. the arbiter pro- grammable options work as follows: channels 0 and 1 are in one group, and channel 2 in the second group. inside the two channel group, the priority can be fixed with a selected channel number having the higher prior- ity, or both can have the same priority in round robin fash- ion. the same scheme applies between the two groups, they can have fixed or round robin priority. in systems with edo dram at 33mhz or page mode dram at 16 to 25mhz that require high bandwidth, the data phase should be extended. in order to extend the data phase, a bi-directional latch should be used. the GT-32090 controls the latch- read output enable (dram data to cpu bus), write output enable (cpu data to dram data), read latch enable (dram data). the latch- ing at the cpu bus is done with the use of the system clock. the correct timing of the controls is derived from the systems parameters - adfreq, type, and latch, which are programmed in the dram parameters regis- ter. 2.6 sio the sio interface is a simple read/write with chip select bus interface. the interface includes: a dedicated 16-bit wide data bus that is shared with the pcmcia devices, an address bus that is shared with the ad bus devices, dedicated byte and 16-bit word address, byte enables (sbe[1:0]*), four chip selects (scs[3:0]*), read (srd*) and write (swr*) control signals, and a flow con- trol signal (swait*), in addition to the dma signals.
GT-32090 system controller for i960jx processors 10 galileo technology, inc. the swait* pin is used to extend a data cycle. two cycles prior to the end of an access, swait* is sampled. if it is asserted, then the access is extended. when swait* is again deasserted, two more cycles will be executed until the end of the data transfer. standard address space is 64mbytes. each of the chip select signals has a 16 mbyte address space, can be configured as 8-bit or 16-bit wide, and has programmable timing. big and little endian conversion is supported for each device. the sio supports up to three slave dma devices as described in section 2.5. further sub-decod- ing can result in four chip selects for a total of 128 mbytes of address space. timing for an sio bus dma or cpu access is program- mable. the user can specify the width of active srd* and swr* signals, and the turn-off time of the device. the width of srd* and swr* dictate the shapes of scs* and dmaack*. they are asserted one cycle before srd* or swr* become active, and remain active for one cycle after srd* or swr* is deasserted. the GT-32090 will not start a new read cycle from a different sio device and will not start a new write access on the sio bus as long as the turn-off time is not satisfied. the turn-off width will start counting when scs* is deasserted to terminal count. when the channel is programmed to word arbitration, a device will be served until all the remaining bytes are packed/unpacked. between accesses, dmaack* will be deasserted for 1 cycle and swr* /srd* for 3 cycles. when the channel is programmed to burst mode with word arbitration, dmaack* will stay asserted through the entire burst. it will be asserted one cycle before srd* (or swr*) becomes active, and remain asserted until one cycle after the last srd* (or swr*) of the burst is deas- serted. the srd* or swr* signals will be asserted for the number of clocks programmed in pulswid and deas- serted for one clock. the partition between the devices is fixed and decoding in the sio is done on address bits 25:24. scs[0]* : address[25:24] = 00 scs[1]* : address[25:24] = 01 scs[2]* : address[25:24] = 10 scs[3]* : address[25:24] = 11 2.7 pcmcia two pcmcia cards can be supported directly by the gt- 32090. each card has a 128mbyte address space dedi- cated to it, 64mbytes for i/o space and 64mbytes for memory space. there is support for big or little endian data formats and 8-bit or 16-bit accesses. the timing of the control signals to the cards is programmable. all the control signals between the cards and the GT-32090 can be connected without glue logic except for the static con- trol and status signals. they are interfaced to the gt- 32090 through an external latch and buffer, as shown in the application section. the partition between pcmcia devices is fixed and decoding is done on address bits 27:26. pcmciaa memory : address[27:26] = 00 pcmciaa i/o : address[27:26] = 01 pcmciab memory : address[27:26] = 10 pcmciab i/o : address[27:26] = 11 2.8 jtag (boundary scan) the GT-32090 supports jtag test features compatible with the ieee standard test access port and boundary scan architecture (ieee 1149.1.a). the jtag features supported are: the GT-32090 idcode is 03290115h. bit[31:28] : version: 0000 bit[27:12] : part number: 0011001010010000 bit[11:1] : manufacturer id: 00010001010 bit[0] : idcodes bit[0] is 1 by definition. boundary scan pins order: all the control signals are active low, that is, the output is enabled when its control signal is "0". test name binary code extest 000 sample 010 idcode 001 stctst 101 intest 100 bypass 111 pad signal chain pos pad type scan type control signal - [145] ctrl norm s_io_oe_buf3_z p/sdata[0] [144] bidir norm s_io_oe_buf3_z p/sdata[1] [143] bidir norm s_io_oe_buf3_z p/sdata[2] [142] bidir norm s_io_oe_buf3_z p/sdata[3] [141] bidir norm s_io_oe_buf3_z p/sdata[4] [140] bidir norm s_io_oe_buf3_z
GT-32090 system controller for i960jx processors 11 galileo technology, inc. p/sdata[5] [139] bidir norm s_io_oe_buf3_z p/sdata[6] [138] bidir norm s_io_oe_buf3_z p/sdata[7] [137] bidir norm s_io_oe_buf3_z p/sdata[8] [136] bidir norm s_io_oe_buf3_z p/sdata[9] [135] bidir norm s_io_oe_buf3_z p/sdata[10] [134] bidir norm s_io_oe_buf3_z p/sdata[11] [133] bidir norm s_io_oe_buf3_z p/sdata[12] [132] bidir norm s_io_oe_buf3_z p/sdata[13] [131] bidir norm s_io_oe_buf3_z p/sdata[14] [130] bidir norm s_io_oe_buf3_z p/sdata[15] [129] bidir norm s_io_oe_buf3_z test* [128] input obsrv rst* [127] input obsrv - [126] ctrl norm adbusgnt_pad_ bst_oe_po adbusgnt [125] 3state norm adbusgnt_pad_ bst_oe_po adbusreq [124] input obsrv - [123] ctrl norm p_test* dmaint[2,0:1]* [122: 120] 3state norm p_test* hold [119] 3state norm p_test* rdyrcv* [118] 3state norm p_test* - [117] ctrl norm ad_en_buf2_z ad[0] [116] bidir norm ad_en_buf2_z ad[1] [115] bidir norm ad_en_buf2_z ad[2] [114] bidir norm ad_en_buf2_z ad[3] [113] bidir norm ad_en_buf2_z ad[4] [112] bidir norm ad_en_buf2_z ad[5] [111] bidir norm ad_en_buf2_z ad[6] [110] bidir norm ad_en_buf2_z ad[7] [109] bidir norm ad_en_buf2_z ad[8] [108] bidir norm ad_en_buf2_z ad[9] [107] bidir norm ad_en_buf2_z ad[10] [106] bidir norm ad_en_buf2_z ad[11] [105] bidir norm ad_en_buf2_z ad[12] [104] bidir norm ad_en_buf2_z ad[13] [103] bidir norm ad_en_buf2_z ad[14] [102] bidir norm ad_en_buf2_z ad[15] [101] bidir norm ad_en_buf2_z ad[16] [100] bidir norm ad_en_buf2_z ad[17] [99] bidir norm ad_en_buf2_z ad[18] [98] bidir norm ad_en_buf2_z ad[19] [97] bidir norm ad_en_buf2_z ad[20] [96] bidir norm ad_en_buf2_z ad[21] [95] bidir norm ad_en_buf2_z pad signal chain pos pad type scan type control signal ad[22] [94] bidir norm ad_en_buf2_z ad[23] [93] bidir norm ad_en_buf2_z ad[24] [92] bidir norm ad_en_buf2_z ad[25] [91] bidir norm ad_en_buf2_z ad[26] [90] bidir norm ad_en_buf2_z ad[27] [89] bidir norm ad_en_buf2_z ad[28] [88] bidir norm ad_en_buf2_z ad[29] [87] bidir norm ad_en_buf2_z ad[30] [86] bidir norm ad_en_buf2_z ad[31] [85] bidir norm ad_en_buf2_z clock [84] input obsrv - [83] ctrl norm p_io_oe1_buf_z be[3:0]* [82:79] bidir norm p_io_oe1_buf_z - [78] input obsrv - [77] ctrl norm p_io_oe0* ale [76] bidir norm p_io_oe0* holda [75] input obsrv w/r* [74] bidir norm p_io_oe0* ads* [73] bidir norm p_io_oe0* - [72] ctrl norm d_test1* le* [71] 3state norm d_test1* lrdoe* [70] 3state norm d_test1* lwroe* [69] 3state norm d_test1* dwr* [68] 3state norm d_test1* ras[3:0]* [67:64] 3state norm d_test1* - [63] ctrl norm d_test0_buf_z cas[3:0]* [62:59] 3state norm d_test0_buf_z - [58] ctrl norm d_test0_i* dadr[0:10] [57:47] 3state norm d_test0_i* ready* [46] input obsrv - [45] ctrl norm p_test_buf_z bufoe* [44] 3state norm p_test_buf_z - [43] ctrl norm d_test1* wren[3:0]* [42:39] 3state norm d_test1* bootcs* [38] 3state norm d_test1* devcs[2:0]* [37:35] 3state norm d_test1* - [34] ctrl norm s_test* scs[3:0] [33:30] 3state norm s_test* dmareq[2:0] [29:27] input obsrv - [26] ctrl norm s_test1* dmaack[2:0]* [25:23] bidir norm s_test1* sbe[1:0]* [22:21] 3state norm s_test* srd* [20] 3state norm s_test* swr* [19] 3state norm s_test* swait* [18] input obsrv pad signal chain pos pad type scan type control signal
GT-32090 system controller for i960jx processors 12 galileo technology, inc. 2.9 reset configuration the GT-32090 must acquire some knowledge of the sys- tem before it is configured by the software. the following configuration pins are sampled from when rst* is asserted, until 4 clock cycles after it is deasserted: dmaack[2:0]* - indicates the three msbs of the gt- 32090 internal address space decode, bits 31:29. these bits are sampled into the internal address space decode & control register bits [5:3]. dmareq[2:0] - indicates the three msbs of the gt- 32090s four devices address, bits 31:29. these bits are sampled into bits [6:4] of the device n address space registers. - [17] ctrl norm sp_test* iowra* [16] 3state norm sp_test* iorda* [15] 3state norm sp_test* wrena* [14] 3state norm sp_test* oea* [13] 3state norm sp_test* cardena[2:1]* [12:11] 3state norm sp_test* waita* [10] input obsrv iowrb* [9] 3state norm sp_test* iordb* [8] 3state norm sp_test* wrenb* [7] 3state norm sp_test* oeb* [6] 3state norm sp_test* cardenb[2:1]* [5:4] 3state norm sp_test* waitb* [3] input obsrv - [2] ctrl norm s_test_z p/saddr[1:0] [1:0] 3state norm s_test_z pad signal chain pos pad type scan type control signal
GT-32090 system controller for i960jx processors 13 galileo technology, inc. 3 register tables the GT-32090s internal registers are memory mapped and can be accessed by the cpu. the registers address is comprised of the value in the internal address space decode and control register and the registers offset. for exam- ple, to access the channel 0 dma byte count register (offset 0x800) immediately after reset, assuming that during reset dmaack[2:0]*s value was 110, the following occurs: the value in the internal address space decode and con- trol register bits [5:0] will be 0x33, which must match the ad bus bits [31:26] as 110011, and the offset being 0x800, will result in a 32-bit address of 0xcc000800. the location of the registers in the memory space can be changed by changing the value programmed into the internal address space decode and control register. for example, after changing the value in this register by writing to 0xcc00001c a value of 0x28, an access to the channel 0 dma byte count register will be with 0xa0000800. the GT-32090s internal registers are 32-bits wide and consequently the appropriate memory region must be config- ured as a 32-bits region, which is done by programming the cpus appropriate pmcon register. 3.1 register map description offset group address space dram address space 0x000 device 0 address space 0x004 device 1 address space 0x008 device 2 address space 0x00c boot device address space 0x010 sio address space 0x014 pcmcia address space 0x018 internal address space decode and control 0x01c dram address space ras[0] decode address 0x400 ras[1] decode address 0x404 ras[2] decode address 0x408 ras[3] decode address 0x40c device address space cs[0] decode address 0x410 cs[1] decode address 0x414 cs[2] decode address 0x418 bootcs decode address 0x41c dram refresh configuration refresh configuration 0x420 dram parameters dram parameters 0x424 device parameters device bank0 parameters 0x428 device bank1 parameters 0x42c device bank2 parameters 0x430 device boot bank parameters 0x434
GT-32090 system controller for i960jx processors 14 galileo technology, inc. dma record channel 0 dma byte count 0x800 channel 1 dma byte count 0x804 channel 2 dma byte count 0x808 channel 0 dma source address 0x810 channel 1 dma source address 0x814 channel 2 dma source address 0x818 channel 0 dma destination address 0x820 channel 1 dma destination address 0x824 channel 2 dma destination address 0x828 channel 0 next record pointer 0x830 channel 1 next record pointer 0x834 channel 2 next record pointer 0x838 dma channel control channel 0 control 0x840 channel 1 control 0x844 channel 2 control 0x848 dma arbiter arbiter control 0x860 sio configuration arbiter control 0xc00 channel flush/reset 0xc04 channel 0 mode 0xc08 channel 1 mode 0xc0c channel 2 mode 0xc10 channel 3 mode 0xc20 pcmcia configuration pcmcia a mode 0xc18 pcmcia b mode 0xc1c
GT-32090 system controller for i960jx processors 15 galileo technology, inc. 3.2 group address space there are eight main address space segments that the GT-32090 decodes. the segments are dram, four ad devices, pcmcia, sio devices, and internal registers. dram address space, offset: 0x000 device 0 address space, offset: 0x004 device 1 address space, offset: 0x008 device 2 address space, offset: 0x00c boot device address space, offset: 0x010 bits field name function initial value 4:0 decode the dram banks will be accessed when ad bits 31:27 match the value programmed in bits 4:0. 0x00 bits field name function initial value 6:0 decode the ad device bank will be accessed when ad bits 31:25 match the value programmed in bits 6:0. {dmareq[2:0],1,1,1,1} * bits [6:4] are sampled during reset from pins dmareq[2:0]. bits field name function initial value 6:0 decode the ad device bank will be accessed when ad bits 31:25 match the value programmed in bits 6:0. {dmareq[2:0],1,1,1,1} * bits [6:4] are sampled during reset from pins dmareq[2:0]. bits field name function initial value 6:0 decode the ad device bank will be accessed when ad bits 31:25 match the value programmed in bits 6:0. {dmareq[2:0],1,1,1,1} * bits [6:4] are sampled during reset from pins dmareq[2:0]. bits field name function initial value 6:0 decode the ad device bank will be accessed when ad bits 31:25 match the value programmed in bits 6:0. {dmareq[2:0],1,1,1,1} * bits [6:4] are sampled during reset from pins dmareq[2:0].
GT-32090 system controller for i960jx processors 16 galileo technology, inc. sio address space, offset: 0x014 pcmcia address space, offset: 0x018 internal address space decode & control, offset: 0x01c bits field name function initial value 4:0 decode the sio banks will be accessed when ad bits 31:27 match the value programmed in bits 4:0. 0x10 bits field name function initial value 3:0 decode the pcmcia cards will be accessed when ad bits 31:28 match the value programmed in bits 3:0. 0xa bits field name function initial value 5:0 decode registers inside the GT-32090 will be accessed when ad bits 31:26 match the value programmed in bits 5:0. {dmaack[2:0]*,0,1,1} * bits [5:3] are sampled during reset from dmaack[2:0]*. 7:6 reserved 8 endian the endianess of the ad bus. this bit is used for reads and writes to internal registers in order to inter- pret correctly the data on the cpu bus upon access to the GT-32090. 0 - little endian 1 - big endian 0x0 9 holdmask masks all requests (i.e. internal dma or external agent) from generating assertion of hold when set. should be set by the cpu only and can be used in critical routines of the cpu. enables the processor to disable all bus and dma requests. 0 - enable requests 1 - mask requests 0x1 10 extown the external agent can own the bus regardless of the state of its adbusreq signal, as long as this bit is set to 1. when set to 1, the GT-32090 asserts hold con- tinuously. set only by the external agent and only when it is master of the bus. 0 - release the bus 1 - own the bus 0x0 11 reserved must be 0 0x0
GT-32090 system controller for i960jx processors 17 galileo technology, inc. 3.3 dram address space the values of the address decode registers determine which physical dram bank will be accessed when the cpu or dma issues an address. the address decoding is done by comparing address bits 25:20 to be equal or higher than the value in the low fields, and equal or lower than the value in the high fields. note that address bit 26 is not a part of the internal decoding and can be used for external decoding to generate two dram banks rass using one GT-32090 ras. ras[0] decode address, offset: 0x400 ras[1] decode address, offset: 0x404 ras[2] decode address, offset: 0x408 ras[3] decode address, offset: 0x40c 3.4 device address space the values of the address decode registers determine which physical device bank will be accessed when the cpu or dma issues an address. the address decoding is done by comparing address bits 24:21 to be equal or higher than the value in the low fields, and equal or lower than the value in the high fields. cs[0] decode address, offset: 0x410 bits field name function initial value 5:0 low lowest decoded address value for ras[0] activation. 0x0 11:6 high highest decoded address value for ras[0] activation. 0x0f bits field name function initial value 5:0 low lowest decoded address value for ras[1] activation. 0x10 11:6 high highest decoded address value for ras[1] activation. 0x1f bits field name function initial value 5:0 low lowest decoded address value for ras[2] activation. 0x20 11:6 high highest decoded address value for ras[2] activation. 0x2f bits field name function initial value 5:0 low lowest decoded address value for ras[3] activation. 0x30 11:6 high highest decoded address value for ras[3] activation. 0x3f bits field name function initial value 3:0 low lowest decoded address value for cs[0] activation. 0x0 7:4 high highest decoded address value for cs[0] activation. 0x1
GT-32090 system controller for i960jx processors 18 galileo technology, inc. cs[1] decode address, offset: 0x414 cs[2] decode address, offset: 0x418 bootcs decode address, offset: 0x41c 3.5 dram refresh configuration this register specifies refresh parameters. the time between dram refresh cycles is programmable, with the option to refresh all the banks at the same time or in staggered fashion. refresh configuration, offset: 0x420 bits field name function initial value 3:0 low lowest decoded address value for cs[1] activation. 0x2 7:4 high highest decoded address value for cs[1] activation. 0x3 bits field name function initial value 3:0 low lowest decoded address value for cs[2] activation. 0x4 7:4 high highest decoded address value for cs[2] activation. 0x5 bits field name function initial value 3:0 low lowest decoded address value for bootcs activation. 0x7 7:4 high highest decoded address value for bootcs activation. 0x7 bits field name function initial value 15:0 refintcnt refresh interval count value. the number of clock cycles between refreshes. the GT-32090 will perform cas before ras refreshes every refintcnt clock cycles. 0xf8 16 stagref staggered refresh. 0 - all the ras signals are asserted simultaneously at refresh. 1 - staggered refresh. 0x0
GT-32090 system controller for i960jx processors 19 galileo technology, inc. 3.6 dram parameters this register specifies the dram timing parameters and the drams refresh type support. the parameter banknref which configures the refresh type support, can be set for each dram bank independently. the dram state machines are optimized to different bus frequencies. in order to control the number of cycles to first data, the adfreq bits should be set according to the bus frequency. dram parameters, offset: 0x424 3.7 device parameters device parameters can be different for each bank. the shape of the different control signals that are active in a device access can be programmed. the access time (in number of cycles) of the device during read accesses should be pro- grammed into the acctofirst field, to set the time data from the device will be ready to be sampled by the cpu or by the GT-32090. acctonext should be programmed with the time data from the device can be sampled in consecutive accesses during burst accesses. the devcs* will be deasserted after the last data is latched and to prevent bus con- tention the turnoff field specifies the number of cycles (from the deassertion of devcs*) to the beginning of the next bus transaction. the write signals pulse can be shaped as well. the parameters specify the number of cycles from the bits field name function initial value 0 type dram type used. 0 - standard page mode 1 - edo 0x0 1 latch defines whether the dram has an external latch on its data lines or not. 0 - no external latch 1 - with external latch 0x0 3:2 adfreq processor bus frequency. 00 - 16mhz 01 - 20mhz 10 - 25mhz 11 - 33mhz 0x11 5:4 bank0ref dram refresh type support. 00 - 1/2k refresh (9 bits row, 9 to 11 bits column) 01 - 1k refresh (10 bits row, 9 to 11 bits column) 10 - 2k refresh (11 bits row, 9 to 11 bits column) 11 - not used 0x0 7:6 bank1ref dram refresh type support. 00 - 1/2k refresh (9 bits row, 9 to 11 bits column) 01 - 1k refresh (10 bits row, 9 to 11 bits column) 10 - 2k refresh (11 bits row, 9 to 11 bits column) 11 - not used 0x0 9:8 bank2ref dram refresh type support. 00 - 1/2k refresh (9 bits row, 9 to 11 bits column) 01 - 1k refresh (10 bits row, 9 to 11 bits column) 10 - 2k refresh (11 bits row, 9 to 11 bits column) 11 - not used 0x0 11:10 bank3ref dram refresh type support. 00 - 1/2k refresh (9 bits row, 9 to 11 bits column) 01 - 1k refresh (10 bits row, 9 to 11 bits column) 10 - 2k refresh (11 bits row, 9 to 11 bits column) 11 - not used 0x0
GT-32090 system controller for i960jx processors 20 galileo technology, inc. beginning of the cycle to the assertion of the write signals (cstowr), the number of cycles the write is active (wrac- tive), and the number of cycles the write signals are inactive (wrhigh) between consecutive writes in a burst access. the ready* signal that can be used to insert wait states to each device data transfer can be enabled/disabled per bank via the ready field. device bank0 parameters, offset: 0x428 device bank1 parameters, offset: 0x42c device bank2 parameters, offset: 0x430 device boot bank parameters, offset: 0x434 bits field name function initial value 1:0 turnoff the number of cycles between the deassertion of devcs* and a new ad bus cycle. 0x3 4:2 acctofirst the number of cycles from devcs* active to first data (determined by the access time of the device). actual value is n+2 (00 is not allowed). 0x7 7:5 acctonext the number of cycles between the sampling of data and the next sampling point of data (time difference between sampling points in a burst sequence). actual value is n+1. 0x7 9:8 cstowr the number of cycles from devcs* to first assertion of wren* actual value is n+2 (00 is not allowed). 0x3 11:10 wractive the number of cycles wren* is active. actual value is n+1. 0x3 13:12 wrhigh the number of cycles between deassertion and assertion of wren*. actual value is n+1 (00 is allowed for 32-bit devices only). 0x3 14 ready controls bus cycle extension, can be disabled by devcs*. 0 - enabled, will extend the bus cycle 1 - disabled 0x0 15 devwidth determines the width configuration for the device. 0 - the device is configured as 8-bits wide. 1 - the device is configured as 16- or 32- bits wide. 0x1 bits field name function initial value 15:0 various fields function as in device bank0. 0xbfff bits field name function initial value 15:0 various fields function as in device bank0. 0xbfff bits field name function initial value 15:0 various fields function as in device bank0. 0xbfff
GT-32090 system controller for i960jx processors 21 galileo technology, inc. 3.8 dma record each dma channel record includes four registers: byte count, source address, destination address, and a pointer to the next record. the active record can be written by the cpu, or by the dma controller in the process of fetching a new record from memory. the structure of the record is illustrated in the following example: channel 0 dma byte count, offset: 0x800 channel 1 dma byte count, offset: 0x804 GT-32090 channel 0 dma registers byte count (bytect) source address (srcadd) destination address (destadd) next record pointer (nextrecptr): 0x10 0x10 bytect 0x14 srcadd 0x18 destadd 0x1c nextrecptr: 0x100 0x100 bytect 0x104 srcadd 0x108 destadd 0x10c nextrecptr: y x bytect x srcadd x destadd x null pointer: 0x0 bits field name function initial value 15:0 bytect the number of bytes that are left in dma transfers. 0x0 bits field name function initial value 15:0 bytect the number of bytes that are left in dma transfers. 0x0 transfer #1 transfer #2 transfer #n
GT-32090 system controller for i960jx processors 22 galileo technology, inc. channel 2 dma byte count, offset: 0x808 channel 0 dma source address, offset: 0x810 channel 1 dma source address, offset: 0x814 channel 2 dma source address, offset: 0x818 channel 0 dma destination address, offset: 0x820 channel 1 dma destination address, offset: 0x824 channel 2 dma destination address, offset: 0x828 bits field name function initial value 15:0 bytect the number of bytes that are left in dma transfers. 0x0 bits field name function initial value 31:0 srcadd the address that the dma controller will read the data from. 0x0 bits field name function initial value 31:0 srcadd the address that the dma controller will read the data from. 0x0 bits field name function initial value 31:0 srcadd the address that the dma controller will read the data from. 0x0 bits field name function initial value 31:0 destadd the address that the dma controller will write the data to. 0x0 bits field name function initial value 31:0 destadd the address that the dma controller will write the data to. 0x0 bits field name function initial value 31:0 destadd the address that the dma controller will write the data to. 0x0
GT-32090 system controller for i960jx processors 23 galileo technology, inc. channel 0 next record pointer, offset: 0x830 channel 1 next record pointer, offset: 0x834 channel 2 next record pointer, offset: 0x838 3.9 dma channel control each dma channel has a control register to set its mode of operation independently of the other two channels. a chan- nel can be programmed to transfer data through the GT-32090 (internal) or directly between dram and devices (fly- by). in the internal mode, the dma reads data from the source address (sio, devices or dram) into an internal 16-byte fifo. from the internal fifo, the data is written to a destination address (sio, devices or dram) that can be indepen- dent from the source address. in fly-by mode, data can be transferred only between a 32-bit wide dram and a 32-bit device through the ad bus. the dma controller will generate addresses for the dram and dmaack* for the device. transfer direction (dram to device or device to dram) has to be programmed in the control registers flybydir field. source addresses and destination addresses can be programmed to increment, decrement, or hold the same value throughout the dma transfer. for devices that can absorb a limited number of bytes at a time, the channel can be pro- grammed to limit the number of bytes transferred in each dma cycle. dma accesses can be initiated by an external source (demand mode) by asserting one of the three dmareq[2:0] pins, or by an internal request (block mode) until the byte count reaches zero. all three channels have chaining support via linked lists of records. when the chaining mode is enabled, the dma con- troller will fetch the information (the record) for a new dma transfer directly out of memory without involving the cpu. the location of the next record is in the next record pointer register (nextrecptr) and the dma controller will fetch records every dma transfer end until it reaches the null pointer (null pointer is zero). there are several mechanisms for status and control of the dma operations. a status interrupt can be programmed to be asserted every time the dma byte count reaches zero, or only when byte count reaches zero and the record is the last record in the chain (the nextrecptr is null). in addition, there is a status bit that indicates whether a channel is active or not. a channel is active when it is enabled and its byte count is other than zero, or in chained mode when both its byte count is not equal to zero or its nextrecptr is not equal to null, or when it is disabled and its internal fifo is not empty . a channel can be controlled by disabling it temporarily, and a next record fetch can be forced in chained mode even if the current dma has not ended. bits field name function initial value 31:0 nextrecptr the address for the next record of dma. a value of 0 means a null pointer (end of the chained list). 0x0 bits field name function initial value 31:0 nextrecptr the address for the next record of dma. a value of 0 means a null pointer (end of the chained list). 0x0 bits field name function initial value 31:0 nextrecptr the address for the next record of dma. a value of 0 means a null pointer (end of the chained list). 0x0
GT-32090 system controller for i960jx processors 24 galileo technology, inc. channel 0 control, offset: 0x840 bits field name function initial value 0 flyby selection of fly-by or normal operation. 0 - no fly-by mode, data is read into the dmas fifo and then written to the destination address. 1 - fly-by mode, data is transferred to/from devices on the ad bus to/from dram 0x0 1 flybydir this bit is meaningful only in fly-by mode. 0 - read from dram 1 - write to dram 0x0 3:2 srcdir source direction. 00 - increment source address 01 - decrement source address 10 - hold in the same value 11 - not allowed 0x0 5:4 destdir destination direction. 00 - increment destination address 01 - decrement destination address 10 - hold in the same value. 11 - not allowed 0x0 8:6 datatranslim data transfer limit in each dma access. 000 - 4 bytes 001 - 8 bytes 011 - 16 bytes 111 - reserved 0x0 9 chainmod chained mode. 0 - chained mode; when a dma access is terminated, the parameters of the next dma access will come from a record in memory that a nextrecptr register points to. 1 - non-chained mode; only the values that are pro- grammed by the cpu directly into the bytect, srcadd, and destadd registers are used. 0x0 10 intmode interrupt mode. 0 - interrupt asserted every time the dma byte count reaches terminal count. 1 - interrupt every null pointer (in chained mode). 0x0 11 transmod transfer mode. 0 - demand 1 - block 0x0 12 chanen channel enable. 0 - disable the channel for dma accesses 1 - enable the channel for dma accesses 0x0
GT-32090 system controller for i960jx processors 25 galileo technology, inc. channel 1 control, offset: 0x844 channel 2 control, offset: 0x848 some extra notes on dma programming follow: - non-chained mode: in this mode, source, destination and byte count should be initialized prior to enabling the channel. chainmod should be set to 1. - chained mode: all the channel records parameters for the current transaction (source, byte count, destination and next record pointer) should be initialized in dram or devices. the address of the first record should be initialized by writing it to the nextrecptr of the channel. the channel should be enabled via chanen=1, the fetnexrec should be set to 1 and the chainmod should be set to 0. - restarting a disabled channel in non-chained mode, chanen should be set to 1. in chained mode, the software should find out if the first fetch took place. if it did, only chanen should be set to 1. if it did not, the fetnexrec should also be set to 1. - reprogramming an active channel the channel should first be disabled via chanen=0. then it must be assured that the channel is no longer active (for example by polling the dmaactst of the channel). new dma parameters should be programmed prior to re-enabling the channel via chanen=1. 13 fetnexrec fetch next record. 0 - normal state (this bit is never written as 0, this is the toggle state after fetch is completed). 1 - forces a fetch of the next record (even if the cur- rent dma has not ended). this bit is reset after fetch is completed (meaningful only in chained mode). 0x0 14 dmaactst dma activity status (read only). 0 - channel is not active 1 - channel is active 0x0 bits field name function initial value 14:0 various fields function as in channel 0 control 0x0 bits field name function initial value 14:0 various fields function as in channel 0 control 0x0 bits field name function initial value
GT-32090 system controller for i960jx processors 26 galileo technology, inc. 3.10 dma arbiter the dma controller has a programmable arbitration scheme between its three channels. the channels are grouped into two groups, one group includes channel 0 and 1, and the other group includes only channel 2. the channels in the first group can be programmed so that one of them will have the higher priority, or they can both have the same priority in round robin fashion. the priority between the two groups can be programmed in a similar way so that a selected group has a higher priority, or they can both have the same priority in round robin. the priority scheme has additional flexibility with the programmable priority option. with the priority option the dma bandwidth allocation can be divided in a fairer way. for example, if the prioopt bit is set to 0 and the priogrps field is set as 10, the requesting devices will get the dma in the order 0,1,2,0,1,2,0,1,2,0,1,2,..... (assuming that priochan1/0 is set to round robin), while if the prioopt bit is set to 1 the requesting devices will get the dma in the order 0,1,0,1,0,1,2,2,2,..... the dma arbiter control register can be reprogrammed any time regardless of the channels sta- tus (active or not active). some arbitration examples follow to facilitate the understanding of this register: 1. assuming all 3 channels are requested all the time, with arbiter control register = 0x40, the order will be: 0,2,1,2,0,2,1,2,0,2,1,2,..... with arbiter control register = 0x0, the order will be: 0,1,2,0,1,2,0,1,2,..... 2. assuming all 3 channels are requested all the time , with arbiter control register = 0x51, the order will be: 2,2,2,2,..1,1,1,1,...,0,0,0,0,..... with arbiter control register = 0x11, the order will be: 2,1,2,0,2,1,2,0,..... 3. assuming all 3 channels are requested all the time, with arbiter control register = 0x50, the order will be: 2,2,2,2,....,1,0,1,0,... with arbiter control register = 0x10, the order will be: 2,0,2,1,2,0,2,1,..... arbiter control, offset: 0x860 bits field name function initial value 1:0 priochan1/0 priority between channel 0 and channel 1. 00 - round robin 01 - priority to channel 1 over channel 0 10 - priority to channel 0 over channel 1 11 - reserved 0x0 3:2 reserved must be 0x0 0x0 5:4 priogrps priority between the group of channels 0&1, and channel 2. 00 - round robin 01 - priority to channel 2 over 0&1 10 - priority to channels 0&1 over 2 11 - reserved 0x0 6 prioopt defines the arbiter behavior for the high priority device. 0 - high priority device will relinquish the bus for a requesting device for one dma transaction. 1 - high priority device will be granted as long as it requests the bus. 0x0
GT-32090 system controller for i960jx processors 27 galileo technology, inc. 3.11 sio configuration these registers configure and control the sio channels. the registers include: the sio local arbiter control register that enables several priority options between the dma channels that are assigned to the sio; the channel flush/reset register that enables the cpu to clear the data from the dma packing and unpacking registers; and the four channel mode registers that define the device parameters (bus width, endianess), the shape of the control signals (pulse width, burst support, turn-off width), and the dma parameters (request polarity, arbitration boundaries, dma direction, dma channel assignment). note that channel 3 does not have dma capabilities nor burst support. channel 3 is for cpu access only. the channel flush/reset register should only be written to the value of 1. after completion of the flush/reset opera- tion, the appropriate bit will be reset to 0. arbiter control, offset: 0xc00 channel flush/reset, offset: 0xc04 bits field name function initial value 1:0 priochan1/0 priority between channel 0 and channel 1. 00 - round robin 01 - priority to channel 1 over channel 0 10 - priority to channel 0 over channel 1 11 - reserved 0x0 3:2 reserved must be 0x0 0x0 5:4 priogrps priority between the group of channels 0&1, and channel 2. 00 - round robin 01 - priority to channel 2 over 0 & 1 10 - priority to channels 0 & 1 over 2 11 - reserved 0x0 6 prioopt defines the arbiter behavior for the high priority device 0 - high priority device will relinquish the bus for a requesting device for one dma transaction. 1 - high priority device will be granted as long as it requests the bus. 0x0 bits field name function initial value 0 flushrstch0 during an sio dma read access, writing 1 will flush the contents of the packing register into the target device on the ad bus. during an sio dma write access, writing 1 will clear the unpacking register. 0x0 1 flushrstch1 field functions as in bit 0. 0x0 2 flushrstch2 field functions as in bit 0. 0x0
GT-32090 system controller for i960jx processors 28 galileo technology, inc. channel 0 mode, offset: 0xc08 bits field name function initial value 0 dmasel selects if the dma is to an sio device or to an ad bus device. 0 - ad bus dma 1 - sio bus dma 0x0 1 buswid the data path width of the device on the sio. 0 - 8-bits 1 - 16-bits 0x0 2 endian defines the device byte ordering. 0 - little endian 1 - big endian 0x0 3 arbbound this bit defines whether the channel arbitrates for the sio bus during a dma operation every access (byte or 16-bit word) or only when the dma is finished pack- ing or unpacking its register. 0 - every access 1 - every word 0x0 4 burstmode selects if the dmaack* corresponding to this channel will stay low through a burst dma or will be deas- serted after every read or write. in burst mode, the strobe signal (i.e. swr*, srd*) is deasserted for one cycle during the access. 0 - dmaack* does not stay low 1 - dmaack* stays low 0x0 5 wrrd defines the dma direction. 0 - read from an sio device 1 - write to an sio device 0x1 9:6 pulswid pulse width, the number of cycles the srd* or swr* signals will be asserted. the actual number will be n+1. 0xf 11:10 towid turn-off width, the number of cycles between the deassertion of the scs* corresponding to this chan- nel in a read access and a) the start of a read cycle to a pcmcia card or to an sio device, or b) a write access to a pcmcia card or an sio device. 0x3 12 dmareqpol selects the polarity of the dmareq signal corre- sponding to this channel. 0 - active high 1 - active low 0x0 13 totalmask when this bit is 1 the corresponding dmareq is masked. 0 - enable dma request. 1 - mask dma request. 0x1 14:17 byteen byte enables of the packing/unpacking register. these bits are read only. this field is only relevant for unpacking. oxf
GT-32090 system controller for i960jx processors 29 galileo technology, inc. channel 1 mode, offset: 0xc0c channel 2 mode, offset: 0xc10 channel 3 mode, offset: 0xc20 3.12 pcmcia configuration the pcmcia mode registers set the timing and device parameters for each pcmcia card. the parameters are the device bus width, the endianess of the device, and the timing of the control signals to the cards. pcmcia a mode, offset: 0xc18 bits field name function initial value 17:0 various fields function as in channel 0. 0x3efe0 bits field name function initial value 17:0 various fields function as in channel 0. 0x3efe0 bits field name function initial value 0 reserved must be 0 0x0 1 buswid the data path width of the device on the sio. 0 - 8-bit 1 - 16-bit 0x0 2 endian defines the device byte ordering. 0 - little endian 1 - big endian 0x0 5:3 reserved 0x0 9:6 pulswid pulse width, the number of cycles the srd* or swr* signals will be asserted. the actual number will be n+1. 0xf 11:10 towid turn-off width, the number of cycles between the deassertion of scs* in a read access and a) the start of a read cycle to a pcmcia card or to an sio device, or b) a write access to a pcmcia card or an sio device. 0x3 bits field name function initial value 0 membuswid selects 8- or 16-bit memory device data width. 0 - 8-bit 1 - 16-bit 0x0 1 i/obuswid selects 8- or 16-bit i/o device data width. 0 - 8-bit 1 - 16-bit 0x0 2 endian defines the pcmcia card byte ordering. 0 - little endian 1 - big endian 0x0
GT-32090 system controller for i960jx processors 30 galileo technology, inc. pcmcia b mode, offset: 0xc1c 3 reserved must be 0. 0x0 7:4 mempulswid the number of cycles oea*, wrena* will be active (the actual number is n+1). 0xf 9:8 memtowid the number of cycles between the deassertion of cardena[2:1]* in a read access and a) the start of a read cycle from the second pcmcia card or from an sio device, or b) a write access to a pcmcia card or an sio device 0x3 11:10 reserved must be 00 0x0 15:12 i/opulswid the number of cycles iowra*, or iorda* will be active (the actual number is n+1). 0xf 17:16 i/otowid the number of cycles between the deassertion of cardena[2:1]* in a read access and a) the start of a read cycle to the second pcmcia card or to an sio device, or b) a write access to a pcmcia card or an sio device. 0x3 bits field name function initial value 17:0 various fields function as in pcmcia a. 0x3f3f0 bits field name function initial value
GT-32090 system controller for i960jx processors 31 galileo technology, inc. 4 restrictions 4.1 cpu interface a) the dram space must be configured as a 32-bit bus in the i960jxs registers. b) the sio and the pcmcia bus must be configured as a 16-bit bus in the i960jxs registers. configuring 8-bit devices is possible by programming the GT-32090s reg- isters only. c) the GT-32090s internal registers space must be con- figured as a 32-bit bus in the i960jxs appropriate pmcon register. 4.2 ad bus device controller a) when signal shaping parameters like wractive, acctofirst, acctonext are programmed to their minimum allowed values, the ready* signal will be ignored during the relevant time. b) the minimum allowed values of the parameters cstowr and acctofirst is 1 (i.e 3 clock cycles). c) the minimum allowed value of the parameter wrhigh is 1 when the device is either 8- or 16-bits wide, and 0 when it is 32-bits wide. 4.3 dma a) dma transactions which involve the sio require the address bits [1:0] of both source and destination to have the same value. b) for dma on the sio bus, when the sio channel is configured to burst mode, source and destination addresses, as well as byte count, must be word-aligned. c) there is dma support only for an ad bus device which is 32-bits wide. d) for each transfer, the minimum byte count is 4. for dma to/from the sio, the field datatranslim in the dma channel control register is restricted to the value 000 - a maximum of 4 bytes. e) in order to restart a channel after it has been enabled, it should first be checked that the dmaactst bit is set to not active (see section 3.9 for details). f) when the source or destination address is decre- mented, both addresses should be word-aligned (that is, a1 and a0 should be both zero), and byte count should be a multiple of 4. g) when using the address hold option in the source direction (srcdir in section 3.9), the source address should be word-aligned. h) when using the address hold option in the destination direction (destdir in section 3.9), both source and desti- nation addresses should be word-aligned. i) records addresses (nextrecptr) should be a multiple of 16. j) in fly-by mode, both source and destination addresses should be word-aligned (that is, a1 and a0 should be both zero), and byte count should be a multiple of 4. k) when the dma is programmed to demand mode (with or without sio channel), first the dma registers should be programmed and then the corresponding sio register (channel mode register). l) for dma on the sio bus, the sio register (channel mode register) should be programmed last in a configu- ration of dma process. in a re-configuration of dma with an sio device this register should be written twice: once with a 0 value to bit 0 (dmasel) and then with a 1 value to that same bit, precisely in this sequence. 4.4 sio & pcmcia a) when the parameter pulswid is programmed to less then 2 (i.e. less then 3 clock cycles) the appropriate wait* signal will be ignored during the assertion of the read or write signals. 4.5 memory mapping a) when the same value is programmed to two or more of the device n address space registers (which configure bits[31:25] of device #ns address space), the regions corresponding to their cs[n] decode address registers (which configure high and low values to bits[24:21] of device #ns address space) must not be overlapped.
GT-32090 system controller for i960jx processors 32 galileo technology, inc. 5 pinout table 5.1 160 pin pqfp (sorted by number) pin # signal name pin # signal name pin # signal name 1 p/sdata[0] 36 ad[3] 71 be[3]* 2 p/sdata[1] 37 ad[4] 72 be[2]* 3 p/sdata[2] 38 ad[5] 73 be[1]* 4 p/sdata[3] 39 ad[6] 74 be[0]* 5 p/sdata[4] 40 ad[7] 75 ale 6 p/sdata[5] 41 ad[8] 76 holda 7 p/sdata[6] 42 ad[9] 77 w/r* 8 p/sdata[7] 43 ad[10] 78 ads* 9 vss 44 ad[11] 79 le* 10 vdd 45 vss 80 lrdoe* 11 p/sdata[8] 46 ad[12] 81 lwroe* 12 p/sdata[9] 47 ad[13] 82 dwr* 13 p/sdata[10] 48 ad[14] 83 ras[3]* 14 p/sdata[11] 49 ad[15] 84 vss 15 p/sdata[12] 50 ad[16] 85 ras[2]* 16 p/sdata[13] 51 ad[17] 86 ras[1]* 17 p/sdata[14] 52 ad[18] 87 ras[0]* 18 p/sdata[15] 53 ad[19] 88 cas[3]* 19 hizall* 54 ad[20] 89 cas[2]* 20 test* 55 ad[21] 90 cas[1]* 21 rst* 56 vss 91 cas[0]* 22 adbusgnt 57 vdd 92 dadr[0] 23 adbusreq 58 ad[22] 93 dadr[1] 24 vss 59 ad[23] 94 dadr[2] 25 vdd 60 ad[24] 95 dadr[3] 26 dmaint[2]* 61 ad[25] 96 vdd 27 dmaint[0]* 62 vdd 97 vss 28 dmaint[1]* 63 vss 98 dadr[4] 29 hold 64 ad[26] 99 dadr[5] 30 rdyrcv* 65 ad[27] 100 dadr[6] 31 ad[0] 66 ad[28] 101 vss 32 ad[1] 67 ad[29] 102 vdd 33 vdd 68 ad[30] 103 dadr[7] 34 vss 69 ad[31] 104 dadr[8] 35 ad[2] 70 vss 105 dadr[9]
GT-32090 system controller for i960jx processors 33 galileo technology, inc. 106 dadr[10] 125 vss 144 waita* 107 ready* 126 vdd 145 iowrb* 108 bufoe* 127 dmaack[2]* 146 iordb* 109 wren[3]* 128 dmaack[1]* 147 wrenb* 110 wren[2]* 129 dmaack[0]* 148 vss 111 vss 130 sbe[1]* 149 vdd 112 wren[1]* 131 sbe[0]* 150 oeb* 113 wren[0]* 132 srd* 151 cardenb[2]* 114 bootcs* 133 swr* 152 cardenb[1]* 115 devcs[2]* 134 swait* 153 waitb* 116 devcs[1]* 135 vss 154 p/saddr[0] 117 devcs[0]* 136 clock 155 p/saddr[1] 118 scs[3]* 137 vdd 156 jtclk 119 scs[2]* 138 iowra* 157 jtrst* 120 scs[1]* 139 iorda* 158 jtms 121 scs[0]* 140 wrena* 159 jtdi 122 dmareq[2] 141 oea* 160 jtdo 123 dmareq[1] 142 cardena[2]* 124 dmareq[0] 143 cardena[1]* pin # signal name pin # signal name pin # signal name
GT-32090 system controller for i960jx processors 34 galileo technology, inc. 6 dc characteristics - preliminary/subject to change 6.1 absolute maximum ratings 6.2 recommended operating conditions 6.3 dc electrical characteristics over operating range (tc=0-70 o c; vdd=+5v, +/-5%) symbol parameter min. max. unit vdd supply voltage -0.3 6.5 v vi input voltage -0.3 vdd+0.3 v vo output voltage -0.3 vdd+0.3 v io output current 24 ma iik input protect diode current +-20 ma iok output protect diode current +-20 ma top operating temperature 0 85 oc tstg storage temperature -40 125 oc esd 2000 v pt power dissipation 1.5 w symbol parameter min. typ. max. unit vdd supply voltage 4.75 5.25 v vi input voltage 0 vdd v vo output voltage 0 vdd v top operating temperature 0 70 oc cin input capacitance 7.2 pf cout output capacitance 7.2 pf symbol parameter test condition min. typ. max. unit vih input high level guaranteed logic high level 2.0 vdd + 0.5v v vil input low level guaranteed logic low level -0.5 0.8 v voh output high voltage ioh = 2 ma ioh = 4 ma ioh = 8 ma ioh = 12 ma ioh = 16 ma ioh = 24 ma 2.4 v
GT-32090 system controller for i960jx processors 35 galileo technology, inc. note: pullup/pulldown resistors are 45kohm minimum, 65kohm typical, 80kohm maximum. vol output low voltage iol = 2 ma iol = 4 ma iol = 8 ma iol = 12 ma iol = 16 ma iol = 24 ma 0.4 v iih input high current +-1 ua iil input low current +-1 ua iozh high impedance output current +-1 ua iozl high impedance output current +-1 ua vh input hysteresis vdd = 4.5v vdd = 5.0v vdd = 5.5v 0.52 0.54 0.56 0.60 0.61 0.62 mv icc operating current 220 ma symbol parameter test condition min. typ. max. unit
GT-32090 system controller for i960jx processors 36 galileo technology, inc. 7 ac timing - preliminary/subject to change (tc= 0-70 o c; vdd= +5v, +/- 5%) notes: 1. all delays, setup, and hold times are referred to clock rising edge, unless stated otherwise. 2. all outputs are specified for 50pf load. 3. all inputs and all outputs also refer to i/o signals behavior. symbol signals description min max unit t1 clock pulse width high 13 ns t2 clock pulse width low 13 ns t3 clock clock period 30 ns t4 clock rise time 3 ns t5 clock fall time 3 ns t6 rst* active 10 clock t7 dadr[10:0], delay from clock rising or falling edge 2 20 ns t7 adbusgnt, dmaack[2:0]*, dmaint[2:0]*, scs[3:0]*, swr*, srd*, p/saddr[1:0], iowra*, iowrb*, iorda*, iordb*, wrena*, wrenb*, oea*, oeb*, cardena[2:1]*, cardenb[2:1]*, w/r*, ads*, hold, rdyrcv*, be[3:0]*, ad[31:0], ras[3:0]*, cas[3:0]*, dwr*, le* (asserted), lrdoe*, lwroe*, bootcs*, devcs[2:0]*, wren[3:0]*, bufoe* delay from clock rising edge 2 15 ns t8 dadr[10:0] delay from clock falling edge 2 20 ns t8 p/sdata[15:0] delay from clock falling edge 2 17 ns t8 sbe[1:0]*, cas[3:0]*, delay from clock falling edge 2 15 ns t8 le* (deasserted) delay from clock falling edge 2 11 ns t9 all inputs setup 10 ns t10 all inputs hold 1 ns t11 all outputs float delay 2 18 ns t12 all outputs drive delay 2 12 ns
GT-32090 system controller for i960jx processors 37 galileo technology, inc. clock voh vol t1 t2 t3 t4 t5 valid inputs setup and hold t9 t10 clock input
GT-32090 system controller for i960jx processors 38 galileo technology, inc. output delay from clock rising edge t7 min clock output t7 max output delay from clock falling edge t8 min t8 max clock output
GT-32090 system controller for i960jx processors 39 galileo technology, inc. output float and drive delay clock valid valid output t11 t12
GT-32090 system controller for i960jx processors 40 galileo technology, inc. 8 functional waveforms addr data1 data2 burst addr1 burst addr2 clock ale ads* rdyrcv* ad[31:0] dadr[1:0] wren[x]* devcs[n]* bufoe* double word write to 32-bit device
GT-32090 system controller for i960jx processors 41 galileo technology, inc. addr data clock ale ads* rdyrcv* ad[31:0] bootcs* bufoe* byte read from 8-bit boot device
GT-32090 system controller for i960jx processors 42 galileo technology, inc. clock ale ads* rdyrcv* w/r* ad[31:0] be[3:0]* dadr[10:0] devcs[2:0]* wren[3:0]* ready* bufoe* 32-bit device write, 2 cycles cs2write, 1 cycle write active/not active
GT-32090 system controller for i960jx processors 43 galileo technology, inc. clock ale ads* rdyrcv* w/r* ad[31:0] be[3:0]* dadr[10:0] devcs[2:0]* wren[3:0]* ready* bufoe* 32-bit device read, 2 cycles to first, 1 cycle delay to next and turn-off
GT-32090 system controller for i960jx processors 44 galileo technology, inc. clock ale ads* rdyrcv* w/r* ad[31:0] be[3:0]* dadr[10:0] devcs[2:0]* wren[3:0]* ready* bufoe* device with maximum delays, 2 bytes write
GT-32090 system controller for i960jx processors 45 galileo technology, inc. clock ale ads* rdyrcv* w/r* ad[31:0] be[3:0]* dadr[10:0] ras[3:0]* cas[3:0]* dwr* standard dram 32-bit write 25 mhz
GT-32090 system controller for i960jx processors 46 galileo technology, inc. ? clock ale ads* rdyrcv* w/r* ad[31:0] be[3:0]* dadr[10:0] ras[3:0]* cas[3:0]* dwr* standard dram 32-bit read 25mhz
GT-32090 system controller for i960jx processors 47 galileo technology, inc. clock ale ads* rdyrcv* w/r* ad[31:0] be[3:0]* dadr[10:0] ras[3:0]* cas[3:0]* dwr* standard dram one byte write 25mhz
GT-32090 system controller for i960jx processors 48 galileo technology, inc. clock ale ads* rdyrcv* w/r* ad[31:0] be[3:0]* dadr[10:0] ras[3:0]* cas[3:0]* dwr* le* lrdoe* lwroe* edo with latch 32-bit write 33mhz
GT-32090 system controller for i960jx processors 49 galileo technology, inc. clock ale ads* rdyrcv* w/r* ad[31:0] be[3:0]* dadr[10:0] ras[3:0]* cas[3:0]* dwr* le* lrdoe* lwroe* edo with latch 32-bit read 33mhz
GT-32090 system controller for i960jx processors 50 galileo technology, inc. clock ale ads* rdyrcv* w/r* ad[31:0] be[3:0]* devcs[2:0]* wren[3:0]* ready* bufoe* dadr[10:0] ras[3:0]* cas[3:0]* dwr* hold holda dmareq[2:0] dmaack[2:0]* dmaint[2:0]* dma burst read from dram
GT-32090 system controller for i960jx processors 51 galileo technology, inc. clock ale ads* ad[31:0] be[3:0]* rdyrcv* hold holda interrupt* devcs[2:0]* dadr[10:0] wren[3:0]* bufoe* ready* dmaack[2:0]* dma write with ready* extending a cycle
GT-32090 system controller for i960jx processors 52 galileo technology, inc. sio dma double 16-bit read in word arbitration mode clock ad[31:0] ads* ale w/r* be[3:0]* rdyrcv* hold holda dadr[10:0] ras[3:0]* cas[3:0]* dwr* dmareq[2:0] dmaack[2:0]* sbe[1:0]* srd* swr* p/sdata[15:0] p/saddr[1:0]
GT-32090 system controller for i960jx processors 53 galileo technology, inc. clock ale ads* rdyrcv* w/r* ad[31:0] be[3:0]* devcs[2:0]* wren[3:0]* ready* bufoe* dadr[10:0] ras[3:0]* cas[3:0]* dwr* hold holda dmareq[2:0] dmaack[2:0]* dmaint[2:0]* dma burst write to an ad bus device
GT-32090 system controller for i960jx processors 54 galileo technology, inc. clock ad[31:0] ads* ale w/r* be[3:0]* rdyrcv* hold holda dadr[10:0] ras[3:0]* cas[3:0]* dwr* dmareq[2:0] dmaack[2:0]* sbe[1:0]* srd* swr* p/sdata[15:0] p/saddr[1:0] sio dma four byte write in burst mode
GT-32090 system controller for i960jx processors 55 galileo technology, inc. clock ale ads* rdyrcv* w/r* ad[31:0] be[3:0]* devcs[2:0]* wren[3:0]* ready* bufoe* dadr[10:0] ras[3:0]* cas[3:0]* dwr* hold holda dmareq[2:0] dmaack[2:0]* dmaint[2:0]* adbusreq adbusgnt dma fly-by mode device to dram burst transfer
GT-32090 system controller for i960jx processors 56 galileo technology, inc. p/sdata[15:0] clock ad[31:0] rdyrcv* ads* ale be[3:0]* i960/width0 i960/width1 scs[3:0]* p/saddr[1:0] sbe[1:0]* swr* srd* 16-bit write to 16-bit sio device
GT-32090 system controller for i960jx processors 57 galileo technology, inc. clock ad[31:0] ads* ale w/r* be[3:0]* rdyrcv* p/saddr[1:0] p/sdata[15:0] cardena[2:1]* oea* wrena* iorda* iowra* cardenb[2:1]* oeb* wrenb* iordb* iowrb* byte write to 8-bit pcmcia memory
GT-32090 system controller for i960jx processors 58 galileo technology, inc. read high byte from 16-bit pcmcia i/o clock ad[31:0] ads* ale w/r* be[3:0]* rdyrcv* p/saddr[1:0] p/sdata[15:0] cardena[2:1]* oea* wrena* iorda* iowra* cardenb[2:1]* oeb* wrenb* iordb* iowrb*
GT-32090 system controller for i960jx processors 59 galileo technology, inc. clock ad[31:0] ads* ale w/r* be[3:0]* rdyrcv* p/saddr[1:0] p/sdata[15:0] cardena[2:1]* oea* wrena* iorda* iowra* cardenb[2:1]* oeb* wrenb* iordb* iowrb* 16-bit write to 16-bit pcmcia i/o
GT-32090 system controller for i960jx processors 60 galileo technology, inc. clock ad[31:0] ads* ale w/r* be[3:0]* rdyrcv* p/saddr[1:0] p/sdata[15:0] cardena[2:1]* oea* wrena* iorda* iowra* cardenb[2:1]* oeb* wrenb* iordb* iowrb* 16-bit read from pcmcia memory
GT-32090 system controller for i960jx processors 61 galileo technology, inc. msb read from 16-bit sio device i960/width0 i960/width1 clock ad[31:0] rdyrcv* ads* ale be[3:0]* scs[3:0]* p/saddr[1:0] sbe[1:0]* swr* srd* p/sdata[15:0]
GT-32090 system controller for i960jx processors 62 galileo technology, inc. 9 applications: connecting the memory buses a GT-32090 system can be assembled in different configurations. the dram has to be 32-bits wide and the devices may be 8-, 16-, or 32-bits wide. the user may choose to work with external latches for the dram (depending on the operating frequency) and can choose to work with a bi-directional transceiver for the devices to reduce turn-off time and the need for drivers on the cpu's ad bus. 9.1 choosing standard dram or edo dram. the choice of which type of memory to use is a function of the performance goals for the system. edo dram, being so common these days, offers an excellent alternative for best performance. be aware of the following restrictions: if working with edo dram at 33 mhz you must use a latch for the data. if working with edo dram at less than 33 mhz you cannot use a latch for the data. if working with standard dram at 33 mhz you cannot use a latch for the data. if working with standard dram at less than 33 mhz you may use a latch for the data (giving you the performance of an edo.) this can be summarized as follows: 9.2 working without data latches/transceivers 9.2.1 dram connection notes: 1. ad[31:24] is always the msb and ad[7:0] is always the lsb, regardless of cpu endianess. memory type frequency latch performance edo 33mhz 25mhz 20mhz 16mhz required not allowed not allowed not allowed xxdddd xdddd dddd dddd dram 33mhz 25mhz 20mhz 16mhz not allowed optional optional optional xxdxdxdxdx xdddd (latches), xxdxdxdxdx (no latches) dddd (latches), xxdxdxdxdx (no latches) dddd (latches), xxdxdxdxdx (no latches) connection memory width connect... to... dram address 32-bit dadr[10:0] dram address pins dram data 1 32-bit ad[31:0] dram data pins dram control 32-bit ras[3:0]* cas[3:0]* dwr* dram ras pins dram cas pins dram write pins
GT-32090 system controller for i960jx processors 63 galileo technology, inc. 9.2.2 device connection notes: 1. ladd[25:2] is the output of the 373 address latches sampled by the ale signal of the cpus ad bus. 2. a2 is the a2 bit of the cpu. 3. ad[31:24] is always the msb and ad[7:0] is always the lsb, regardless of endianess. 4. ad[15:8] is always the msb and ad[7:0] is always the lsb, regardless of endianess. 5. wren[3]* is for ad[15:8], wren[0]* is for ad[7:0]. 9.3 working with data latches/transceivers 9.3.1 dram connection notes: 1. ad[31:24] is always the msb and ad[7:0] is always the lsb, regardless of cpu endianess. 2. must have a 32 bi-directional latch (such as 2 idtfct16543). connection memory width connect... to... device address 32-bit 16-bit 8-bit { ladd[24:4] 1 , dadr[1:0] } { ladd[24:3] 1 , a2 2 , be[1]* } { ladd[24:2] 1 , be[1:0]* } device address pins device address pins device address pins device data 32-bit 16-bit 8-bit ad[31:0] 3 ad[15:0] 4 ad[7:0] device data pins device data pins device data pins device control 32-bit 16-bit 8-bit wren[3:0]* wren[3]*, wren[0]* 5 wren[0]* device write pins device write pins device write pins connection memory width connect... to... dram address 32-bit dadr[10:0] dram address pins dram data 1,2 32-bit ad[31:0] latch i/os a side latch i/os b side dram data pins dram control 32-bit ras[3:0]* cas[3:0]* dwr* 0 0 lwroe* lrdoe* clock le* dram ras pins dram cas pins dram write pins ceab* of 543 data latches ceba* of 543 data latches oeba* of 543 data latches oeab* of 543 data latches leba* of 543 data latches leab* of 543 data latches
GT-32090 system controller for i960jx processors 64 galileo technology, inc. 9.3.2 device connection notes: 1. ladd[25:2] is the output of the 373 address latches sampled by the ale signal of the cpus ad bus. 2. a2 is the a2 bit of the cpu. 3. ad[31:24] is always the msb and ad[7:0] is always the lsb, regardless of endianess. 4. ad[15:8] is always the msb and ad[7:0] is always the lsb, regardless of endianess. 5. wren[3]* is for ad[15:8], wren[0]* is for ad[7:0]. connection memory width connect... to... device address 32-bit 16-bit 8-bit { ladd[24:4] 1 , dadr[1:0] } { ladd[24:3] 1 , a2 2 , be[1]* } { ladd[24:2] 1 , be[1:0]* } device address pins device address pins device address pins device data 32-bit 16-bit 8-bit ad[31:0] 3 transceiver i/os b side ad[15:0] 4 transceiver i/os b side ad[7:0] transceiver i/os b side transceiver i/os a side device data pins transceiver i/os a side device data pins transceiver i/os a side device data pins device control 32-bit 16-bit 8-bit wren[3:0]* bufoe* w/r* wren[3]* , wren[0]* 5 bufoe* w/r* wren[0]* bufoe* w/r* device write pins oe* of 16245 transceiver dir of 16245 transceiver device write pins oe* of 16245 transceiver dir of 16245 transceiver device write pins oe of 16245 transceiver dir of 16245 transceiver
GT-32090 system controller for i960jx processors 65 galileo technology, inc. 10 system configurations the basic GT-32090 system shown below includes 4 banks of 32-bit wide dram, 32-bit devices, two pcmcia slots, and 8- or 16-bit devices on the sio bus. in this system, data can be moved via dma between ad bus devices and dram, between sio devices and dram, and between sio devices and ad bus devices. GT-32090 i960jx dram dadr[10:0] cas[3:0]* ras[0]* dwr* le* lrdoe* 16543 oeab* leab* leba* oeba* b a clock 16373 ale ad[31:0] control 16245 w/r* bufoe* (rom, wren[3:0]* devcs[2:0]*, bootcs* sbe[1:0]* scs[3:0]* swr* srd* sio devices ad bus devices iowra*, iorda* wrena*, oea* waita*, cardena[2:1]* iowrb*, iordb* wrenb*, oeb* waitb*, cardenb[2:1]* pcmcia card a pcmcia card b externa l master adbusreq adbusgnt flash, sram, i/o, etc.) lwroe* 32 a b dir oe* {ladd[24:4], dadr[1:0]}
GT-32090 system controller for i960jx processors 66 galileo technology, inc. 10 package 10.1 160-pin quad flat package (qfp, eiaj)
GT-32090 system controller for i960jx processors 67 galileo technology, inc. 10.2 160 - pin quad flat package expanded view (qfp, eiaj) fig. 10.2 : expanded view galileo technology, inc. 1735 n. first st. #308 san jose, ca 95112 usa tel (408) 451-1400 fax (408) 451-1404

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